Quarter-square Analog Four-Quadrant Multiplier Using Mos Integrated Circuit Technology
Pena-finol, Jesus S.
Connelly, Joseph A.
MetadataShow full item record
A four-quadrant NMOS transconductance multiplier including plural NMOS transistors formed in a substrate to produce a pair of summer stages and a pair of squaring stages which process a pair of input signals V1, V2 to produce an output signal Vo according to the quarter-square algebraic identity, Vo =1/4[(V1 +V2)2 -(V1 -V2)2 ]=V1 V2.In a preferred embodiment, the substrate doping NA =6.7X10^15 cm-3 and the channel width and channel length of each of the NMOS transistors forming the summer and squaring stages is greater than 10 ?m.
- Georgia Tech Patents