Power, Performance, and Cost Impact of Gate-level Monolithic 3D IC in the 7nm Technology Node

Abstract

The nature of device scaling in the 7nm era is changing from the traditional scheme driven by Moore’s law because of the physical and economic limitations of fabrication. Instead of reducing a horizontal distance between devices to increase the density of system functionalities, concerted efforts for 3D integration have been made from both industries and academic fields to utilize the vertical dimension to increase the chip density.

Over the last few years, monolithic 3D (M3D) technology, which involves the integration of one or more active layers on top of a prefabricated metal stack in monolithic fashion, has emerged as a promising solution for the massive 3D interconnection. The objective of this research is to study the impact of M3D technology on the power, performance and cost of integrated circuits under unique challenges of M3D technology in the 7nm node.

The most critical challenge in M3D integration is that once the bottom tier devices and interconnects are implemented with the normal process, they suffer from additional thermal exposure during the dopant activation step of the top tier. Therefore, alternative fabrication steps and materials for each tier are required. The first section of this thesis presents the physical design methodologies to tackle the inter-tier variations in 2-tier M3D ICs, and shows the power and performance benefits of M3D ICs in various scenarios.

Although M3D integration offers the small form factor, low power, and high system performance, high fabrication cost is another challenge to justify the adoption of M3D technology. The second section investigates the complicated power, performance, and cost (PPC) tradeoffs of 2-tier M3D ICs based on the accurate wafer and die cost models along with the optimal CAD solution for M3D ICs to maximize the area and routing utilization of designs.