Architecting High-Performance, Efficient, and Scalable Heterogeneous Memory Systems with 3D-DRAM

Abstract

Advancements in packaging technology enable high-bandwidth 3D-DRAM that mitigates the memory bandwidth wall. With the integration of 3D-DRAM and high-capacity memory, heterogeneous memory systems are able to satisfy the high memory-bandwidth demand of processors. However, traditional management techniques developed for on-chip caches are neither suitable nor efficient for heterogeneous memory: they fail to maximize the benefits provided by 3D-DRAM and thus deliver sub-optimal performance. To address the performance gap, this dissertation investigates the deficiencies of conventional techniques and proposes simple and effective architectural innovations that improve performance. The dissertation develops the techniques at various levels of the memory system: managing only 3D-DRAM for bandwidth efficiency and run-time adaptability, coordinating 3D-DRAM and commodity DRAM for the resource utilization of bandwidth and capacity, and scaling the system to multiple nodes.