3D and 2.5D heterogeneous integration platforms with interconnect stitching and microfluidic cooling
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Signal integrity and thermal management are the two major challenges in heterogeneous integration technologies. In this research, the impact of through silicon vias (TSVs) on electrical performance of 3D/2.5D ICs was experimentally investigated. It was found the delay of the 3D IC link can be improved by proper TSV placement and scaling. To address the thermal challenges, embedded microfluidic cooling was proposed and two testbeds were fabricated and characterized with two-phase cooling. The maximum heat transfer coefficient was up to 60 kW/m2K. To avoid the shortcomings of conventional heterogeneous integration technologies, a heterogeneous interconnect stitching technology (HIST) platform was proposed. Two HIST testbeds with fine-pitch microbumps and compressible microinterconnects (CMIs) were demonstrated and the signal performance of the HIST channel was investigated. The insertion loss of a HIST channel was measured to be 0.85 dB/mm at 50 GHz. Lastly, the inductance and capacitance of the CMIs were experimentally characterized from 250 MHz to 50 GHz.