• Login
    View Item 
    •   SMARTech Home
    • Georgia Tech Theses and Dissertations
    • Georgia Tech Theses and Dissertations
    • View Item
    •   SMARTech Home
    • Georgia Tech Theses and Dissertations
    • Georgia Tech Theses and Dissertations
    • View Item
    JavaScript is disabled for your browser. Some features of this site may not work without it.

    Single-phase liquid cooling for thermal management of power electronic devices

    Thumbnail
    View/Open
    AGBIM-THESIS-2017.pdf (3.920Mb)
    Date
    2017-07-31
    Author
    Agbim, Kenechi Aretha
    Metadata
    Show full item record
    Abstract
    Power electronic devices such as MOSFETs, HEMTs, and IGBTs often face reliability challenges due to poor thermal management during device operation at high power densities. In the conventional approach, such devices are packaged on power electronic substrates (e.g., direct bonded copper (DBC)) which is then attached to heat spreaders and ultimately cold plates to remove dissipated thermal energy. Thus, there are several critical layers that add to the thermal resistance of the overall design that limit the heat dissipation from power electronic devices. By eliminating layers, the integration of liquid cooling techniques has shown promise to significantly reduce (up to 25% reduction) in the thermal resistance in power electronic cooling systems as compared to the thermal resistance found using a conventional cold plate cooler design. Thus, the main objective of this work is to evaluate vertical (perpendicular fluid flow) and horizontal (parallel fluid flow) cooling schemes with integrated cooling on the backside of the DBC substrate. The cooling systems in this work utilize directly integrated cooling of electronics (DICE) techniques with enhanced heat transfer through microstructured features integrated into the DBC. For this work, each cooling method underwent a pseudo-optimization design analysis to identify the relevant contributors to the performance of the heat sink designs. Parameters such as pressure drop, pumping power, and heat transfer coefficient were used to assess industry and manufacturing tradeoffs associated with each design. Through experiments, the pressure drop, chip junction temperature, and inlet and outlet temperatures were measured and will be presented. To validate the experimental results, numerical and analytical models were developed to simulate the experimental environment and will be presented. Finally, the prospects for integrating these techniques into real power electronic packaging architectures will be discussed.
    URI
    http://hdl.handle.net/1853/58752
    Collections
    • Georgia Tech Theses and Dissertations [23877]
    • School of Mechanical Engineering Theses and Dissertations [4086]

    Browse

    All of SMARTechCommunities & CollectionsDatesAuthorsTitlesSubjectsTypesThis CollectionDatesAuthorsTitlesSubjectsTypes

    My SMARTech

    Login

    Statistics

    View Usage StatisticsView Google Analytics Statistics
    facebook instagram twitter youtube
    • My Account
    • Contact us
    • Directory
    • Campus Map
    • Support/Give
    • Library Accessibility
      • About SMARTech
      • SMARTech Terms of Use
    Georgia Tech Library266 4th Street NW, Atlanta, GA 30332
    404.894.4500
    • Emergency Information
    • Legal and Privacy Information
    • Human Trafficking Notice
    • Accessibility
    • Accountability
    • Accreditation
    • Employment
    © 2020 Georgia Institute of Technology