Negative Capacitance Technology for Ultra-low Power Computing

Abstract

Negative capacitance - an unusual physical phenomenon, where the stored charge decreases with an increasing voltage - can find interesting applications in electronics. For example, when used as the gate oxide in the MOSFET, a negative capacitance material can reduce the subthreshold swing below the fundamental physical limit of 60 mV/decades [1]. This device technology can, in turn, significantly lower the energy dissipation in CMOS circuits by enabling new pathways for arbitrarily reducing the power supply voltage. I will give an overview of the exciting developments in the field of negative capacitance over the past six years starting from the theoretical prediction in 2008 to the clean experimental demonstration of this phenomenon in archetypal ferroelectric oxides [2,3]. I will also discuss our recent experimental work on negative capacitance transistors [4] and energy and performance projections of circuits based on negative capacitance MOSFETs [5,6,7]

References: [1] Salahuddin et al. "Use of negative capacitance to provide voltage amplification for low power nanoscale devices." Nano Letters 8, 405 (2008). [2] Khan et al. “Negative capacitance in a ferroelectric capacitor.” Nature Mater. 14, 182 (2015). [3] Khan et al. “Experimental evidence of ferroelectric negative capacitance in nanoscale heterostructures.” Appl. Phys. Lett. 99, 113501 (2011). [4] Khan et al. “Negative capacitance in short-channel FinFETs externally connected to an epitaxial ferroelectric capacitor.” IEEE Electron Dev. Lett. 367, 111 (2016). [5] Khan et al. “Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation.” Proc. IEEE Electron Devices Meeting (IEDM), pp. 11-3 (2015). [6] Khandelwal, S., et al. "Circuit performance analysis of negative capacitance FinFETs." Proc. IEEE Symp. VLSI Technology (2016). [7] Samal et al. “Full chip power benefits with negative capacitance FETs.” Proc. ISLPED (2017).