Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines

Abstract

The energy-efficiency and security needs in computing systems, ranging from high performance processors to low-power devices are steadily increasing. State-of-the-art digital systems use dedicated encryption hardware for compute intensive steps requiring encryption. These encryption engines are vulnerable to different forms of side channel attacks (SCA). Traditional countermeasures to protect against such attacks suffer from high power and performance overheads, diminishing system energy-efficiency. Integrated voltage regulators (IVR) are an integral part of energy-efficient digital systems. As inductive IVRs isolate the side channel signatures of an encryption engine from the measured side channel signatures at the IVR input, they can be potentially exploited for improvement in power SCA (PSCA) resistance. Moreover the presence of an inductance, a strong electromagnetic (EM) radiator, in an inductive IVR can potentially improve EMSCA resistance as well. This thesis investigates the design of an inductive IVR for improving side channel resistance of an encryption engine.

The IVR transformations that modify the side channel signatures from an encryption engine are identified and a simulation framework is used to quantify the improvement in PSCA resistance at the input of an illustrative IVR. A test-chip, containing an all-digital IVR architecture, a security aware block called Loop Randomization (LR) inside the IVR and a 128-bit Advanced Encryption Standard (AES) engine is fabricated in 130nm CMOS. Measurement results from the test-chip with an active LR demonstrates improved resistance to a Correlation Power Attack (CPA) and no leakage in Test Vector Leakage Assessment (TVLA) in the power signature at the IVR input. The proposed security aware IVR design also improves system EMSCA resistance, quantified through CPA and TVLA. The proposed security aware IVR design modifications are all-digital, synthesizable, seamlessly integrable into the existing IVR architectures and incurs minimal overhead on the system area/power/performance.