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dc.contributor.advisorMukhopadhyay, Saibal
dc.contributor.authorKar, Monodeep
dc.date.accessioned2018-01-22T21:07:38Z
dc.date.available2018-08-01T11:00:30Z
dc.date.created2017-08
dc.date.issued2017-09-25
dc.date.submittedAugust 2017
dc.identifier.urihttp://hdl.handle.net/1853/59182
dc.description.abstractThe energy-efficiency and security needs in computing systems, ranging from high performance processors to low-power devices are steadily increasing. State-of-the-art digital systems use dedicated encryption hardware for compute intensive steps requiring encryption. These encryption engines are vulnerable to different forms of side channel attacks (SCA). Traditional countermeasures to protect against such attacks suffer from high power and performance overheads, diminishing system energy-efficiency. Integrated voltage regulators (IVR) are an integral part of energy-efficient digital systems. As inductive IVRs isolate the side channel signatures of an encryption engine from the measured side channel signatures at the IVR input, they can be potentially exploited for improvement in power SCA (PSCA) resistance. Moreover the presence of an inductance, a strong electromagnetic (EM) radiator, in an inductive IVR can potentially improve EMSCA resistance as well. This thesis investigates the design of an inductive IVR for improving side channel resistance of an encryption engine. The IVR transformations that modify the side channel signatures from an encryption engine are identified and a simulation framework is used to quantify the improvement in PSCA resistance at the input of an illustrative IVR. A test-chip, containing an all-digital IVR architecture, a security aware block called Loop Randomization (LR) inside the IVR and a 128-bit Advanced Encryption Standard (AES) engine is fabricated in 130nm CMOS. Measurement results from the test-chip with an active LR demonstrates improved resistance to a Correlation Power Attack (CPA) and no leakage in Test Vector Leakage Assessment (TVLA) in the power signature at the IVR input. The proposed security aware IVR design also improves system EMSCA resistance, quantified through CPA and TVLA. The proposed security aware IVR design modifications are all-digital, synthesizable, seamlessly integrable into the existing IVR architectures and incurs minimal overhead on the system area/power/performance.
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technology
dc.subjectSide channel attack
dc.subjectPower attack
dc.subjectDifferential power analysis
dc.subjectDPA
dc.subjectCorrelation power analysis
dc.subjectCPA
dc.subjectDifferential electromagnetic analysis
dc.subjectDEMA
dc.subjectTest vector leakage assessment
dc.subjectTVLA
dc.subjectIntegrated voltage regulators
dc.subjectIVR
dc.subjectVoltage regulation
dc.subjectHaswell
dc.subjectFIVR
dc.subjectSecurity guard extension
dc.subjectSGX
dc.subjectDC-DC converters
dc.subjectBuck regulators
dc.subjectIoT
dc.subjectCountermeasures
dc.subjectAdvanced encryption standard
dc.subjectAES
dc.subjectAES-NI
dc.subjectRandomization
dc.subjectSecurity
dc.subjectMasking countermeasure
dc.subjectDual rail logic
dc.titleExploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines
dc.typeDissertation
dc.description.degreePh.D.
dc.contributor.departmentElectrical and Computer Engineering
dc.embargo.terms2018-08-01
thesis.degree.levelDoctoral
dc.contributor.committeeMemberBeyah, Raheem
dc.contributor.committeeMemberRaychowdhury, Arijit
dc.contributor.committeeMemberDe, Vivek
dc.contributor.committeeMemberKumar, Satish
dc.date.updated2018-01-22T21:07:38Z


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