Thermal and power delivery network modeling for emerging microelectronic integration platforms
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In this dissertation, thermal management and power delivery challenges in 2.5-D and 3-D integration are presented. To address the thermal coupling issues in heterogeneous 3-D ICs, a new stacking structure is proposed using interposer embedded microfluidic cooling and air gap isolation. To understand the thermal design constraints of 2.5-D integration, thermal exploration is performed for three approaches of 2.5-D integration. Moreover, the impact of several different technology parameters is studied, such as die thickness mismatch and die spacing. Next, power supply challenges are investigated focusing on bridge-chip based 2.5-D integration. Because the bridge chips underneath the active dice block access to package power/ground planes in 2.5-D bridge-chip based integration, there are higher supply voltage noise in these regions. Several approaches are proposed to reduce the supply voltage noise. In addition, to accurately model temperature, power supply noise and power dissipation, an integrated thermal and power delivery modeling framework considering the interactions between them is developed. Lastly, signal propagation delay and energy per bit of the digital communication channels of 2.5-D and 3-D integration are benchmarked and compared using compact circuit modeling. The impact of technology scaling, pad size, interconnect length, and temperature are studied and investigated.