Thermal-driven Circuit Partitioning and Floorplanning with Power Optimization

Abstract

In this paper, we present methodology to distribute the temperature of gates evenly on a chip while simultaneously reducing the power consumption by using newly designed partitioning and floorplanning algorithms. This new partitioning algorithm is designed to partition blocks with well-balanced temperatures by altering the FM algorithm to include thermal constraints. Then, the suggested floorplanning algorithm can assign specific geometric locations to the blocks to refine the quality of the thermal distribution and to reduce power consumption. The combination of these two new algorithms, called TPO, is compared with the results of a conventional design procedure. As a result, power is reduced by up to 19% on average and a well-distributed thermal condition is achieved.