Physical Layout Automation for System-On-Packages

Abstract

System-On-Package (SOP) paradigm proposes a unified chip-plus-package view of the design process, where heterogeneous system components such as digital ICs, analog/RF ICs, memory, optical interconnects, MEMS, and passive elements (RLC) are all packaged into a single high speed/density multi-layer SOP substrate. We propose a new chip/package co-design methodology for physical layout under the new SOP paradigm. This new methodology enables the physical layout design and analysis across all levels of the SOP design implementation, bridging gaps between IC design, package design, and package analysis to efficiently address timing closure and signal integrity issues for high-speed designs. In order to accomplish a rigorous performance and signal integrity optimization, efficient static timing analysis (STA), signal integrity analysis (SIA), and thermal and power analysis (TPA) tools are fully integrated into our co-design flow. Our unified wire-centric physical layout toolset that includes on-chip/package wire generation, on-chip/package floorplanning, and on-chip/package wire synthesis provides wire solutions for all levels of the design hierarchy-including cell, block, and chip level for pure digital and mixed signal environment. In addition, on-chip hard/soft IP (Intellectual Property) integration is supported in our co-design flow for shorter design times through design reuse. To the best of our knowledge, this paper is the first to address the chip/package co-design issues in System-On-Package (SOP) physical layout