• Login
    View Item 
    •   SMARTech Home
    • Center for Experimental Research in Computer Systems (CERCS)
    • CERCS Technical Reports
    • View Item
    •   SMARTech Home
    • Center for Experimental Research in Computer Systems (CERCS)
    • CERCS Technical Reports
    • View Item
    JavaScript is disabled for your browser. Some features of this site may not work without it.

    Simultaneous Delay and Power Optimization for Multi-level Partitioning and Floorplanning with Retiming

    Thumbnail
    View/Open
    git-cercs-03-08.pdf (120.0Kb)
    Date
    2003
    Author
    Ekpanyapong, Mongkol
    Lim, Sung Kyu
    Metadata
    Show full item record
    Abstract
    Delay minimization and power minimization are two important objectives in the design of the high-performance, portable, and wireless computing and communication systems. Retiming is a very effective way for delay optimization for sequential circuits. In this paper we propose a unified framework for multi-level partitioning and floorplanning with retiming, targeting simultaneous delay and power optimization. We first discuss the importance of retiming delay and visible power as opposed to the conventional static delay and total power for sequential circuits. Then we propose GEO-PD algorithm for simultaneous delay and power optimization and provide smooth cutsize, wirelength, power and delay tradeoff. In GEO-PD, we use retiming based timing analysis and visible power analysis to identify timing and power critical nets and assign proper weights to them to guide the multi-level optimization process. In general, timing and power analysis are done at the original netlist while a recursive multi-level approach performs partitioning and floorplanning on the sub-netlist as well as its coarsened representations. We show an effective way to translate the timing and power analysis results from the original netlist to a coarsened sub-netlist for effective multi-level delay and power optimization. To the best of our knowledge, this is the first paper addressing simultaneous delay and power optimization in multi-level partitioning and floorplanning.
    URI
    http://hdl.handle.net/1853/5927
    Collections
    • CERCS Technical Reports [193]

    Browse

    All of SMARTechCommunities & CollectionsDatesAuthorsTitlesSubjectsTypesThis CollectionDatesAuthorsTitlesSubjectsTypes

    My SMARTech

    Login

    Statistics

    View Usage StatisticsView Google Analytics Statistics
    facebook instagram twitter youtube
    • My Account
    • Contact us
    • Directory
    • Campus Map
    • Support/Give
    • Library Accessibility
      • About SMARTech
      • SMARTech Terms of Use
    Georgia Tech Library266 4th Street NW, Atlanta, GA 30332
    404.894.4500
    • Emergency Information
    • Legal and Privacy Information
    • Human Trafficking Notice
    • Accessibility
    • Accountability
    • Accreditation
    • Employment
    © 2020 Georgia Institute of Technology