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dc.contributor.authorBalakrishnan, Karthik
dc.contributor.authorNanda, Vidit
dc.contributor.authorEkpanyapong, Mongkol
dc.contributor.authorLim, Sung Kyu
dc.date.accessioned2005-03-24T19:20:23Z
dc.date.available2005-03-24T19:20:23Z
dc.date.issued2003
dc.identifier.urihttp://hdl.handle.net/1853/5934
dc.description.abstractDelay and wirelength minimization continue to be important objectives in the design of high-performance computing systems. For large-scale circuits, the clustering process becomes essential for reducing the problem size. However, to the best of our knowledge, there is no study about the impact of multi-level clustering on performance-driven global placement. In this paper, five clustering algorithms including the quasi-optimal retiming delay driven PRIME and the cutsize-driven ESC have been considered for their impact on state-of-the-art mincut based global placement. Results show that minimizing cutsize or wirelength during clustering typically results in significant performance improvements.en
dc.format.extent544129 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technologyen
dc.relation.ispartofseriesCERCS;GIT-CERCS-03-16
dc.subjectCutsizesen
dc.subjectDelay optimizationen
dc.subjectDesignen
dc.subjectHigh performance computingen
dc.subjectLarge-scale circuitsen
dc.subjectMulti-level clusteringen
dc.subjectPerformance improvementen
dc.subjectPerformance-driven global placementen
dc.subjectSurveysen
dc.subjectWirelengthen
dc.subjectClustering
dc.titleImpact of Multi-level Clustering on Performance Driven Global Placementen
dc.typeTechnical Reporten


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