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dc.contributor.authorNanda, Vidit
dc.contributor.authorBalakrishnan, Karthik
dc.contributor.authorEkpanyapong, Mongkol
dc.contributor.authorLim, Sung Kyu
dc.date.accessioned2005-03-29T14:31:32Z
dc.date.available2005-03-29T14:31:32Z
dc.date.issued2003
dc.identifier.urihttp://hdl.handle.net/1853/5944
dc.description.abstractThe recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wiring length. However, the problem of thermal dissipation is magnified due to the nature of these layered technologies. In this paper, we develop techniques to reduce both the local and global congestions of 3D circuit designs in order to alleviate thermal issues. Our approach consists of two phases. First, we use a multilevel min-cut based approach with a modified gain function in order to minimize the local congestion. Then, we perform simulated annealing to reduce the circuit's global congestion. Experimental results show that our local congestion is reduced by an average of over 44% and global congestion is reduced by over 16%. Moreover, we only see an 11% increase in the wiring length and the number of vias required.en
dc.format.extent611077 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technologyen
dc.relation.ispartofseriesCERCS;GIT-CERCS-03-27
dc.subject3D IC technology
dc.subjectGain function
dc.subjectGlobal congestion of 3D circuit designs
dc.subjectLocal congestion of 3D circuit designs
dc.subjectMincut-based global placement
dc.subjectSimulated annealing
dc.subjectThermal dissipation
dc.subjectWirelength
dc.subjectThermal issues
dc.titleCongestion-Driven Global Placement for Three Dimensional VLSI Circuitsen
dc.typeTechnical Reporten


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