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dc.contributor.authorEkpanyapong, Mongkol
dc.contributor.authorMinz, Jacob Rajkumar
dc.contributor.authorWatewai, Thaisiri
dc.contributor.authorLee, Hsien-Hsin Sean
dc.contributor.authorLim, Sung Kyu
dc.date.accessioned2005-03-29T19:35:19Z
dc.date.available2005-03-29T19:35:19Z
dc.date.issued2003
dc.identifier.urihttp://hdl.handle.net/1853/5952
dc.description.abstractAs process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communication within a single cycle, thus decaying the performance scalability substantially. An effective floorplanning algorithm can no longer ignore the information of dynamic communication patterns of applications. In this paper, using the profile information acquired at the architecture/microarchitecture level, we propose a "profile-guided microarchitectural floorplanner" that considers both the impact of wire delay and the architectural behavior, namely the inter-module communication, to reduce the latency of frequent routes inside a processor and to maintain performance scalability. Based on our simulation results, the profile-guided method shows a 5% to 40% IPC improvement when clock frequency is fixed. From the perspective of instruction throughput (in BIPS), our floorplanner is much more scalable than a conventional wire length based floorplanner.en
dc.format.extent198956 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technologyen
dc.relation.ispartofseriesCERCS;GIT-CERCS-03-28
dc.subjectDeep submicron processorsen
dc.subjectDeep submicron technologiesen
dc.subjectFloorplanningen
dc.subjectIntra-chip communicationen
dc.subjectLatencyen
dc.subjectProfile-guided microarchitectural floorplanneren
dc.subjectScalabilityen
dc.subjectThroughputsen
dc.subjectWire delays
dc.titleProfile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Designen
dc.typeTechnical Reporten


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