Design and test methodologies with statistical analysis for reliable memory and processor implementations
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The object of the proposed research is to develop comprehensive methodologies, including circuit design, new test methodologies, and statistical failure analysis, to implement reliable microprocessor and main memory systems. For a microprocessor, we have focused on the reliability issues in the embedded cache, since SRAMs are designed with the tightest design rules, and high performance processors are expected to consist of a large embedded memory. Also, to solve the scaling challenges for the main memory system, we have studied optimized design schemes for the 3D DRAM system, to achieve better performance, reliability, cost, and power.