Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system
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The objective of this research is to extract NBTI and GOBD model parameters to enable the estimation of the degradation and the remaining life of individual chips. Also, the performance degradation can predict lifetime as well, and can enable the optimization of timing guardbands or circuit adaptation based on a prediction of the increase in delay as a function of time, temperature, and usage. Based on the performance degradation analysis, we design a yield and reliability tolerant system by using a self-adaptive clock duty cycle controller (DCC) system to avoid timing violations of critical paths in an integrated circuit.