Now showing items 1-2 of 2
A broadband passive delay line structure in 0.18 micron CMOS for a gigabit feed forward equalizer
(Georgia Institute of Technology, 2004-11-01)
This project focusses on the design of a high speed passive delay line for use in a Feed Forward Equalizer (FFE). The FFE is used to equalize a 20 Gbp/s throughput PAM-4 signal after transmission through a 20-inch FR4 ...
A Novel Analog Decision-Feedback Equalizer in CMOS for Serial 10-Gb/sec Data Transmission Systems
(Georgia Institute of Technology, 2007-11-02)
This dissertation develops an unclocked receiver analog decision-feedback equalizer (ADFE) circuit architecture and topology and implements the circuit in 0.18-um CMOS to enable 10-Gb/sec serial baseband data transmission ...