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dc.contributor.advisorMa, Xiaoli
dc.contributor.authorWen, Qingsong
dc.date.accessioned2018-05-31T18:32:40Z
dc.date.available2018-05-31T18:32:40Z
dc.date.issued2017-03-27
dc.date.submittedMay 2017
dc.identifier.urihttp://hdl.handle.net/1853/59966
dc.description.abstractLenstra-Lenstra-Lovasz (LLL) algorithm has been adopted as a lattice reduction (LR) technique for multiple-input multiple-output (MIMO) systems in wireless communications to improve performance with low complexity. Recently, some enhanced LLL variants are proposed, such as greedy LLL algorithms with fast convergence and fixed-complexity LLL (fcLLL) algorithms with constant hardware run-time. However, the existing greedy LLL and fcLLL algorithms are still inefficient which do not fully exploit the inherent characteristics of LLL algorithms. In this dissertation, we present enhanced greedy LLL and fcLLL algorithms for LR-aided MIMO detectors, which deal with the shortcomings in the existing greedy LLL and fcLLL algorithms. Furthermore, we implement the proposed enhanced fcLLL algorithm in FPGA by two types of architectures for low complexity and high throughput, respectively. Both simulations and implementations show that the proposed algorithms and architectures exhibit much better performance than the state-of-the-art solutions.en_US
dc.language.isoen_USen_US
dc.publisherGeorgia Institute of Technologyen_US
dc.subjectLattice reductionen_US
dc.subjectLLLen_US
dc.subjectMIMO detectionen_US
dc.subjectFPGA implementationen_US
dc.titleEfficient LLL-based lattice reduction for MIMO detection: From algorithms to implementationsen_US
dc.typeDissertationen_US
dc.description.degreePh.D.
dc.contributor.departmentElectrical and Computer Engineering
thesis.degree.levelDoctoral
dc.contributor.committeeMemberChang, Gee-Kung
dc.contributor.committeeMemberBaxley, Robert J.
dc.contributor.committeeMemberLi, Geoffrey Ye
dc.contributor.committeeMemberXie, Yao


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