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dc.contributor.advisorBakir, Muhannad
dc.contributor.authorMohseni, Javaneh
dc.date.accessioned2018-08-20T15:33:44Z
dc.date.available2018-08-20T15:33:44Z
dc.date.created2018-05
dc.date.issued2018-08-15
dc.date.submittedMay 2018
dc.identifier.urihttp://hdl.handle.net/1853/60192
dc.description.abstractIn multi-core systems, the memory latency and bandwidth are among the key limitations. While interconnects have created major challenges for the integrated circuit technology in the past decades, there have been major changes in the nature and the severity of the challenges in recent years. Therefore, modeling and benchmarking the interconnect performance for memory chips is of utmost importance. The memory system design is facing many challenges. DRAM-based memory systems are stretched to meet the increasing demands on high memory bandwidth and large memory capacity that are required by multi-core processors. To address these challenges both technology and circuit solutions should be investigated. While this work focuses on a few memory technologies, the modeling approach presented here and the insights obtained regarding the limits and opportunities associated with interconnects apply to other emerging and conventional memory technologies.
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technology
dc.subjectMemory
dc.subjectInterconnect
dc.subjectPerformance modeling
dc.titlePerformance modeling and optimization for on-chip interconnects in memory arrays
dc.typeDissertation
dc.description.degreePh.D.
dc.contributor.departmentElectrical and Computer Engineering
thesis.degree.levelDoctoral
dc.contributor.committeeMemberNaeemi, Azad
dc.contributor.committeeMemberDavis, Jeffrey
dc.contributor.committeeMemberBrand, Oliver
dc.contributor.committeeMemberJoshi, Yogendra
dc.date.updated2018-08-20T15:33:44Z


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