Variation-aware and process-sensitive reliability simulator and its application for analog and digital circuits

Abstract

A reliability simulator for traditional gate oxide time dependent dielectric breakdown (TDDB) and the newly emerged middle-of-line (MOL) TDDB in both digital and analog circuits’ is built. A methodology and its corresponding algorithms to extract vulnerable features for gate oxide time dependent dielectric breakdown and middle-of-line (MOL) TDDB for both bulk CMOS and FinFET technology are proposed. Combined with vulnerable features, a circuits’ activity profile and temperature map are used for the lifetime calculation of the circuit. Process variation and its impact on circuit lifetime are also investigated. With the simulator built, the optimal test regions for estimating both mechanisms can be found. The optimization framework of analog circuit based on performance, area and lifetime trade-off is also discussed.