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dc.contributor.advisorMilor, Linda
dc.contributor.advisorChatterjee, Abhijit
dc.contributor.authorYang, Kexin
dc.date.accessioned2019-01-16T17:23:25Z
dc.date.available2019-01-16T17:23:25Z
dc.date.created2018-12
dc.date.issued2018-10-29
dc.date.submittedDecember 2018
dc.identifier.urihttp://hdl.handle.net/1853/60762
dc.description.abstractA reliability simulator for traditional gate oxide time dependent dielectric breakdown (TDDB) and the newly emerged middle-of-line (MOL) TDDB in both digital and analog circuits’ is built. A methodology and its corresponding algorithms to extract vulnerable features for gate oxide time dependent dielectric breakdown and middle-of-line (MOL) TDDB for both bulk CMOS and FinFET technology are proposed. Combined with vulnerable features, a circuits’ activity profile and temperature map are used for the lifetime calculation of the circuit. Process variation and its impact on circuit lifetime are also investigated. With the simulator built, the optimal test regions for estimating both mechanisms can be found. The optimization framework of analog circuit based on performance, area and lifetime trade-off is also discussed.
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technology
dc.subjectTime-dependent dielectric breakdown
dc.subjectLifetime simulator
dc.subjectWearout
dc.subjectFrontend-of-line dielectric breakdown
dc.subjectGate oxide breakdown
dc.subjectMiddle-of-line breakdown
dc.subjectDigital circuit
dc.subjectMicroprocessor
dc.subjectReliability
dc.titleVariation-aware and process-sensitive reliability simulator and its application for analog and digital circuits
dc.typeDissertation
dc.description.degreePh.D.
dc.contributor.departmentElectrical and Computer Engineering
thesis.degree.levelDoctoral
dc.contributor.committeeMemberNaeemi, Azad
dc.contributor.committeeMemberYu, Shimeng
dc.contributor.committeeMemberZhou, Hao-Min
dc.date.updated2019-01-16T17:23:25Z


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