Digitally-assisted, efficiency enhanced, linear RF power amplifier architectures

Abstract

This dissertation presents the use of advanced digital techniques in the development of efficiency enhanced, linearized power amplifier (PA) architectures. In this research, digital enhancements are used to boost the efficiency of a dual-input LDMOS Doherty PA of 500W peak power. It is shown that the improved phase adjustment and the waveform conditioning for the Auxiliary PA, results in ~ 4% improvement in the efficiency of the Doherty PA. This efficiency improvement comes at the cost of degradation in linearity. A new segmented DPD architecture is proposed which subdivides the complete dynamic range of the Doherty PA into two power regions, a lower and a higher power region. As the nature of non-linearities exhibited by the Doherty PA are different in these distinct regions, the segmented DPD architecture is found suitable in this scenario. It is shown that by using the segmented DPD architecture, stringent linearity requirement of -55 dBc is adequately met.