Power and performance optimization of negative capacitance transistor circuits

Abstract

Negative Capacitance Field Effect Transistor (NCFET) is an emerging technology solution for achieving extremely low power and high performance. The negative capacitance exhibited by the ferroelectric layer of the transistor results in very high effective gate capacitance leading to electrostatic voltage amplification. In other words, the internal gate voltage is extremely amplified facilitating low sub-threshold slopes and enhanced drain-currents. Therefore, NCFET tremendously reduces power consumption by enabling extremely low voltage operation. Whereas the enhanced current behavior of NCFET enables extremely high-performance improvement. The NCFET characteristics depend on various parameters such as the ferroelectric properties and operating voltage. In this work, the effects of ferroelectric parameters on device characteristics are exhaustively analyzed at various operating voltages. The power and performance exploration is then extended to logic gate and full-chip designs. The characteristics of several logic gates are carefully studied to associate observed power-performance effects with root-cause parameters. Two full-chip benchmarks, a cell-dominated and a wire-dominated design are used for full-chip analysis in order to obtain a generic understanding of the negative capacitance effects. The multi-level comprehensive NCFET analysis provides a counter-intuitive design guideline: NCFET with the lowest sub-threshold slope may not provide minimum power consumption or maximum performance. Under certain conditions, such NCFETs actually deteriorate power consumption and performance compared to NCFETs with a higher sub-threshold slope. The NCFET power analysis shows that power consumption depends on a combination of factors such as operating voltage, NCFET transfer characteristics, and threshold voltage in addition to sub-threshold slope. Further, the comprehensive multi-voltage multilevel analysis also reveals a notion of optimal ferroelectric parameter and operating voltage combination for iso-performance maximum power reduction. An NCFET with certain ferroelectric properties can be associated with an optimal voltage and for a given operating voltage a certain set of optimal ferroelectric parameters provide maximum power reduction. At a given operating voltage, the feasible NCFETs with low current enhancement provide maximum power reduction. The optimal NCFETs are also influenced by design type as the wire-dominated benchmark is observed to exhibit relatively higher power reduction where the excess current is utilized for driving longer wires decreasing buffer requirement. At an operating voltage of VDD = 0.4 V, the optimal NCFET is shown to yield 78% iso-performance total power reduction compared to the baseline operating at VDD = 0.8 V. NCFETs with enhanced drain currents are desirable for improving performance. But the negative capacitance effect abruptly increases both drain current and gate capacitance at low gate voltages. The effective delay is determined by the ratio of the gate capacitance and drain current (t = Q/I) at the operating voltage of interest. NCFETs exhibiting high drain current operate faster at low voltages. As voltage increases, the NCFETs with less abrupt transfer characteristics start providing lower delay due to low capacitance overhead. Certain high-performance NCFETs lose negative capacitance enhancement at higher gate voltages, leading to additional performance deterioration. Therefore, the ferroelectric parameters providing maximum drain current constitute the minimum delay region at extremely low voltage which gradually shifts towards NCFETs with lower drain current enhancement as voltage increases. Energy-delay-product (EDP) optimization is considered to collectively optimize both performance and power. Feasible NCFETs with low drain current provide the maximum power reduction leading to distinct high performance and low power NCFETs. Optimal EDP reduction is provided by a distinct subset of NCFETs between the above two. As voltage increases, both high-performance and optimal EDP regions shift towards low drain current NCFETs as they become faster. At an operating voltage of VDD = 0.4 V, the optimal NCFET is shown to yield more than a node improvement with 61% total power reduction and 44% performance improvement compared to the baseline operating at VDD = 0.8 V.