Theoretical and experimental investigations of connectivity in three-dimensional integrated circuits

Abstract

Three-dimensional integration, in which integrated circuits (ICs) are stacked directly atop one another to reduce interconnect length, is an attractive method for achieving continued performance and efficiency improvements as conventional 2D scaling slows. Significant uncertainty remains, however, about the best methods and designs to adopt for optimal system performance and energy efficiency. In order to address these questions, we present improved interconnect and system-level models for 3D IC performance, as well as experimental investigations into potential thermal limits to the stacking of high performance components. Improved modeling methods for ultra-densely-interconnected systems will also be discussed, in order to quantify the performance impacts of restricted connectivity on complex systems.