Performance estimation of large area nanowires

Abstract

The focus of the thesis is to extensively model high-performance nanowires, develop Verilog A models of the devices and then simulate them using SPICE to estimate their power-performance trade-offs. Once the device models are created, they will be used in circuits which will have realistic interconnects with necessary parasitic resistance and impedance (inductance and capacitance) and simulated for prototypical digital and mixed signal designs. The device and the circuit simulation infrastructure will be developed in parallel. Synopsys Taurus and Medici will be used for 3D device modelling, Verilog A for circuit-compatible models, and Spice for circuit and system evaluation.