Development of compliant free-standing structures for sub 32-nm multi-core ICs
Sitaraman, Suresh K.
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With the introduction of on-chip low-K dielectric materials, it is increasingly important to reduce on-chip stresses so that the low-K dielectric material will not crack or delaminate. One way to reduce the thermo-mechanical stresses is to introduce compliant structures between the die and the substrate and thus to decouple the die from the substrate. Decoupling the die from the substrate or the substrate from the board by means of mechanically compliant interconnects will reduce stresses created by the coefficient of thermal expansion mismatch. A decoupled diesubstrate or substrate-board interface will allow the different components to expand or contract differently without inducing high stresses in the components. In this work, we report the design, fabrication, modeling, and characterization of innovative multi-path fan-shaped off-chip compliant interconnects. The proposed interconnects can be fabricated at the wafer-level and are cost-effective, can be of fine pitch and scalable, and will have redundant electrical paths.