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dc.contributor.authorChatterjee, Abhijit
dc.date.accessioned2019-07-03T18:57:37Z
dc.date.available2019-07-03T18:57:37Z
dc.date.issued2012-06
dc.identifier.urihttp://hdl.handle.net/1853/61488
dc.descriptionIssued as final reporten_US
dc.description.abstractA low cost post-manufacturing testing and speed tuning methodology is proposed in a multi-processor system. The goal of this research is to develop a methodology that allows the “safe” speed of each core in a large CMP to be determined under the assumption that some speed defects and design bugs are likely to escape conventional delay testing procedures.en_US
dc.description.sponsorshipNational Science Foundation (U.S.)en_US
dc.language.isoen_USen_US
dc.publisherGeorgia Institute of Technologyen_US
dc.relation.ispartofseriesSchool of Electrical and Computer Engineering ; Project no. 110093en_US
dc.subjectMulti-core systemsen_US
dc.subjectMultiprocessorsen_US
dc.titleTargeting multi-core clock performance gains: vertically integrated adaptation and prototypingen_US
dc.typeTechnical Reporten_US
dc.contributor.corporatenameGeorgia Institute of Technology. Office of Sponsored Programsen_US
dc.contributor.corporatenameGeorgia Institute of Technology. School of Electrical and Computer Engineeringen_US


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