A holistic study of on-chip interconnect technology: From modeling theory to physical design of semiconductor ICs

Abstract

The objective of this research is to present a holistic study of the on-chip copper interconnect technology, from interconnect modeling to their manifestation in modern design implementations in the advanced technology landscape. With technology scaling, interconnects have become critical to optimal design and technology enablement; therefore, interconnect analysis and optimization is of utmost importance. Cu/low-k interconnects are studied in physical designs based on high-performance FinFET in the advanced technology nodes. While severe size-effects of copper rapidly increase wire resistance, FinFET technology further magnifies its contribution to the circuit delay. An alternate interconnect sizing is proposed that alleviates wire resistance at the cost of wire capacitance. This wire sizing proposal is demonstrated to improve the circuit performance upto 2x. Furthermore, lithography regimes utilized to pattern advanced interconnects (e.g., LELE and SAQP) induce large variability in interconnect resistance. A novel hybrid patterning regime is proposed, to reduce the variability in interconnect resistance and improve circuit yield. An optimal interconnect design is deduced for low-power designs based on the FDSOI and TFET architectures at the advanced process nodes. In particular, the circuit performance and power is optimized. The circuit study of TFET technology at the physical-design level reveals that these circuits are less impacted by the interconnect resistance problem and more sensitive to interconnect capacitance. A popular interconnect modeling regime based on Rent's rule is re-evaluated for its applicability to system-level modeling of modern designs in the advanced technology landscape. The historical Rent's methods are found to be inaccurate, and a modernized Rent's model is proposed to capture the rapidly evolving facets of VLSI design. Modernized Rent-based interconnect models are derived to exhibit improved calibration with data from a suite of commercial processors, forming a strong foundation for faithful design and technology benchmarking and pathfinding.