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dc.contributor.advisorTummala, Rao
dc.contributor.advisorAntoniou, Antonia
dc.contributor.authorShahane, Ninad Makarand
dc.date.accessioned2019-08-21T13:49:11Z
dc.date.available2019-08-21T13:49:11Z
dc.date.created2018-08
dc.date.issued2018-07-27
dc.date.submittedAugust 2018
dc.identifier.urihttp://hdl.handle.net/1853/61634
dc.description.abstractThe objectives of this work are to design and demonstrate novel chip-to-package substrate Cu-based interconnections without solders at 20µm pitch for power handling at current densities exceeding 10E5 A/cm2, high-throughput manufacturability, and thermomechanical reliability without cracking low-K on-chip dielectrics. To realize these objectives, two approaches are proposed, based on design of nanoscale bonding interfaces for assembly throughput, and electrical, thermal and reliability performances. The first approach utilizes novel Au-based bimetallic thin-films applied on Cu bumps and pads to prevent oxidation and enhance bonding reactivity. This approach focuses on thin-film interdiffusion in nanocrystalline Cu-Ni/Pd-Au layers and the reaction kinetics behind intermetallic compound (IMC) formation at the bonded interfaces. A high-speed thermocompression assembly process is developed and validated to boost throughput. Furthermore, the stability of these interconnection systems is demonstrated through extensive thermomechanical and electro migration reliability testing. The second approach introduces low-modulus nanocopper foam caps on bulk Cu micro-bumps to act as compliant and reactive bonding interfaces. A fundamental understanding of this sintering process is proposed and contrasted to that of conventional nanoparticle-based systems. Using co-electrodeposition techniques, patterned nano-Cu foam capped interconnections are fabricated and a first assembly of such compliant interconnections is demonstrated. In conclusion, these unique Cu interconnection technologies address cost, manufacturability, and scalability and therefore, have the potential to become the next interconnection nodes for high-performance systems.
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technology
dc.subjectInterconnections
dc.subjectFlipchip
dc.subjectMetallurgy
dc.subjectNanocopper foams
dc.subjectNanoporous
dc.subjectThermocompression bonding
dc.subjectReliability
dc.subjectSintering
dc.titleReliable fine-pitch chip-to-substrate copper interconnections with high-through assembly and high power-handling
dc.typeDissertation
dc.description.degreePh.D.
dc.contributor.departmentMaterials Science and Engineering
thesis.degree.levelDoctoral
dc.contributor.committeeMemberThadhani, Naresh
dc.contributor.committeeMemberSingh, Preet
dc.contributor.committeeMemberSmet, Vanessa
dc.contributor.committeeMemberRaj, P. M.
dc.date.updated2019-08-21T13:49:11Z


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