On-die adaptive power regulation and distribution for digital loads

Abstract

The objective of this dissertation is to provide a power architecture solution where guardband reduction and consistent performance are the key goals for power delivery networks in multicore SoCs. The necessity for maximizing energy efficiency without compromising performance has led to the implementation of fine-grain Dynamic Voltage and Frequency Scaling (DVFS). However, as DVFS schemes support ever-increasing supply-frequency operating points, static and dynamic variations result in increasing design guard-bands and impact the system power efficiency. The research work presented here will attempt to address these concerns through multiple approaches geared towards the different components in the power delivery network hierarchy. SoC power delivery network designs are typically application and specification oriented. As such, there are several design perspectives and for each perspective, many permutations of implementation exist. Hence, a single unified solution for the entire hierarchical PDN is impractical and not feasible. Therefore, in this thesis the approach followed is to optimize and enhance the various components that constitute the PDN with the governing notion being to enable system designers to move away from worst-case to adaptive designs. The underlying theme across all the designs is to sense the dynamic nature of digital loads and, based on it, make intelligent choices in the mode of the converter or regulator that would eventually lead to a more power efficient design. These various approaches are focused primarily on integrated LDOs and Switched capacitor (SC) converters. The key topics that will be discussed are digital assists for analog LDOs, a novel approach of integrating clocking and supply voltage loops and elastic and multiple output switched capacitor networks, that will include theoretical models and measurements from silicon test-chips. For the different techniques discussed in this thesis the design, analysis, and verification have been performed through test-chips built in scaled CMOS processes.