Automated I/O library generation for interposer based system-in-package integration of multiple heterogeneous dies

Abstract

System-in-Package (SiP) integration of multiple dies in a single package can achieve much higher performance than on-board integration of ICs while reducing the design cost/effort compared to large System-on-Chips (SoCs). However, a major challenge in design of SiPs with many dies is automated design and insertion of Input/Output (I/O) cells to minimize energy and delay of the wire traces. The research presents an automated cell library generation flow for all-digital I/O circuits for SiP integration. Given parameterized models of SiP wire traces, our method automatically designs, optimizes, and generates layouts of I/O cells for delay/energy minimization. The proposed flow is demonstrated on interposer based SiP integration considering 28nm CMOS technology and 65nm BEOL technology. Given a multi-die SiP design and associated interposer wire-traces, the research demonstrates that automated I/O library cell generation can reduce maximum die-to-die communication delay or energy. The research demonstrate the proposed flow for various interposer parameters and SiP designs to show the feasibility of chip-interposer co-design.