Energy efficient architectures for irregular data streams
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An increasing prevalence of data-irregularity is being seen in applications today, particularly in machine learning, graph analytics, high-performance computing and cybersecurity. Faced with fundamental technology constraints, architectures that have been designed around conventional assumptions on spatio-temporal locality are inefficient for these important domain areas. This PhD thesis finds that energy efficiency and performance of such data irregular applications can be improved via near memory and near processor sparse data stream acceleration and address remapping. In particular, this thesis proposes computer architectures that improve energy efficiency and performance by intelligently reducing data movement through the memory hierarchy for applications that exhibit data-irregularities due to sparse accesses or due to computationally error-tolerant post-Moore processing.