An FPGA implementation of adaptive linearization of power amplifiers
Ahluwalia, Sehej Swaran
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Power amplifiers (PAs) are inherently nonlinear devices; utilized in essentially all communication systems around the world. An ideal, linear, PA would take an input signal and simply provide a constant gain; resulting in minimal distortion of the input. However, due to their nonlinear characteristics at higher input powers, these amplifiers end up producing a higher power output that is not a perfect amplified version of the input. Which can lead to information loss in communication systems. Digital predistortion is a popular method of reducing the nonlinear effects of these devices. The algorithm works by modifying the incoming signal before it reaches the amplifier. This modification is designed in such a way that the nonlinear effects are cancelled out after the signal is sent through the PA. Due to the constant changing nature of power amplifiers these algorithms need to be adaptive as to guarentee performance over various conditions. The approach discussed in this thesis develops a gradient descent direct learning architecture that is implemented entirely in the fabric of an FPGA. The proposal attempts to utilize the parallel computing power of an FPGA along with their high clock and data rates, in order to create a faster adaptive system. The effectiveness of this development is demonstrated via simulations in MATLAB, Simulink and VHDL. The algorithm shows more accurate and more stable results than other predistorter approaches as well as faster adaptive convergence times. The results and comparisons of the various implementations are discussed in this work. Continued development of this approach could allow for faster more robust digital predistorter implementations in a variety of applications.