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dc.contributor.advisorSarkar, Vivek
dc.contributor.authorViszlai, Joshua
dc.date.accessioned2020-11-09T17:00:42Z
dc.date.available2020-11-09T17:00:42Z
dc.date.created2020-05
dc.date.submittedMay 2020
dc.identifier.urihttp://hdl.handle.net/1853/63889
dc.description.abstractThis research looks at the register allocation phase of a compiler for programs running on a RISC-V machine. Register allocation algorithms were applied to a test program compiled through an LLVM-based toolchain to be run on a RISC-V simulator. Four register allocation algorithms were used in compilation of the libquantum test case from the SPECint2006 CPU test suite. The number of loads and stores when executed on a RISC-V simulator were observed, and the results showed that a large determinant of performance was the extent of saving and restoring registers during function calls.
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technology
dc.subjectCompiler
dc.subjectRISC-V
dc.subjectLLVM
dc.titleAn Analysis of Register Allocation Techniques in the Context Of A RISC-V Processor
dc.typeUndergraduate Research Option Thesis
dc.description.degreeUndergraduate
dc.contributor.departmentComputer Science
dc.contributor.departmentComputer Science
thesis.degree.levelUndergraduate
dc.contributor.committeeMemberZhao, Jisheng
dc.date.updated2020-11-09T17:00:42Z


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