CHARACTERIZATION OF LIBRARY CELLS FOR OPEN AND SHORT CIRCUIT DEFECT EXPOSURE: A SYSTEMATIC METHODOLOGY
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With the advancement in technology scaling and voltage scaling, achieving a high defect coverage is a major challenge for the IC test industry. Traditional gate-level test methods using fault models such as stuck-at and transition faults have proven to be insufficient for detecting intra-cell open and short circuit defects. Cell-Aware test methodology has shown to improve the defect coverage for such defects with limited magnitudes (due to simulation overhead) using a single pattern and two pattern tests. Further, more than two pattern test can be required to detect subtle defects due to effects such as charge sharing. In this work, circuit simulations are used to expose defect locations and sizes that can escape the current test methods, and identify the patterns that can detect them. Additionally, an algorithmic methodology to characterize cell input stimuli to detect the defects faster than simulation-based defect detection.