• Future Branches -- Beyond Speculative Execution 

      Appelbe, William F.; Das, Raja; Harmon, C. Reid, Jr. (Georgia Institute of Technology, 1997)
      Speculative execution of conditional branches has a high hardware cost, is limited by dynamic branch prediction accuracies, and does not scale well for increasingly superscalar architectures. Future branches are ...
    • Instructions Scheduling for Highly Super-scalar Processors 

      Appelbe, William F.; Das, Raja; Harmon, C. Reid, Jr. (Georgia Institute of Technology, 1997)
      Super-scalar processors can execute multiple instructions out-of-order per cycle and speculatively execute instructions through branches. Such processors invalidate many of the assumptions of traditional instruction ...
    • IPU/LTB: A Method for Reducing Effective Memory Latency 

      Harmon, C. Reid, Jr.; Appelbe, William F.; Das, Raja (Georgia Institute of Technology, 1997)
      This paper describes a new hardware approach to data and instruction prefetching for superscalar processors. The key innovation is instruction prefetching by predicting procedural control flow, and decoupling data and ...