Clock Network Design for 2.5D Heterogeneous Systems
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The CMOS process technology scaling may have reached its pinnacle, yet not all ele- ments of computing can be manufactured at lower technological nodes. This has led to the development of a new branch of chip designing that allows chiplets on different technolog- ical nodes to be integrated on to a single package using interposers, the passive intercon- nection mediums. However, establishing a high-frequency communication over an entirely passive layer is one of the significant design challenges of 2.5D systems. My research will focus on building a robust clocking architecture for 2.5D systems, using a 64 core processor benchmark. The clocking scheme of any 2.5D design consists of two major components, viz., Interposer Clocking, and On-Chiplet Clocking. The interposer clocking consists of clocks used to achieve global synchronicity and clocks for inter-chiplet communication es- tablished using AIB protocol. These clocking components will be built using commercial EDA tools and analyzed using standard tools, and package/interconnect models. I will also be comparing these results against a 2D design of the same benchmark and against a differ- ent 2.5D clocking architecture to study if the 2.5D clock network can be designed to offer better power performance than the 2D counterpart.