Understanding the Design Space of Dataflows for Graph Neural Network Accelerators
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Deep Neural Networks (DNNs) have enabled numerous applications like Image Classification, Speech Recognition, Natural Language Processing, Robotics, Recommendation Systems etc. However, DNN algorithms like Convolutional Neural Networks (CNNs) and Recurrent Neural Networks (RNNs) are not capable of learning arbitrary data representations. Graph Neural Networks (GNNs) are becoming popular due to their success at learning irregular data which can be represented by graphs. GNNs consist of 2 phases - (1) an irregular (memory intensive) phase known as Aggregation where the information is aggregated from the neighbours, and (2) a regular (compute intensive) phase known as Combination for reduction of feature vector size. These operations cannot be handled efficiently by the conventional CPUs and GPUs. Consequently, dedicated GNN accelerators have been proposed which use particular dataflows for each phase(intra-phase) and different communication strategies between the two phases(inter-phase). Prior works on GNN Accelerators propose different optimizations in hardware and software in order to efficiently run Graph Neural Networks. These works propose specific intra-phase and inter-phase dataflows, microarchitecture, graph partitioning technique and different ways to handle sparsity. However, since the number of applications and their underlying GNN algorithms are increasing, it is important to design future proof GNN accelerators. It is necessary to understand the impact of different design choices on the desired metrics like performance and energy and to understand the design-space of the GNN accelerators before making design decisions. This work aims at understanding the design space of GNN dataflows and proposes a systematic approach to classify the dataflows and quantitatively model the trade-offs. There are various kinds of design choices like hardware parameters, graph partitioning techniques, dataflows, handling sparsity etc. In this work we specifically focus on the design space of GNN dataflows. We model our cycle accurate simulation infrastructure OMEGA for modelling GNN accelerators by making modifications to the simulator STONNE which models DNN accelerators. We also build an analytical model around STONNE to obtain relevant statistics related to different inter-phase dataflows. We propose a taxonomy to describe and classify different GNN dataflows and characterize the performance and energy of different GNN dataflows on different GNN workloads. We also describe the hardware capabilities that are required to support different GNN dataflows. We choose representative mappings from the search space and evaluate the design parameters affecting the performance and energy of dataflows using our simulation infrastructure and we report our insights and takeaways from the evaluations. We analyze the impact of different inter-phase and intra-phase dataflow design parameters on different workloads. A structured approach to understand the impact of GNN dataflows will enable systematic design of future GNN accelerators. A systematic insight into the design space of GNN dataflows will also lead to design of mapping optimizers for GNNs.