Bus Interconnect Structure for a System-on-a-Chip Multiprocessor System
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This report describes two possible implementations for a bus interconnect structure which would be used in a multiprocessor System-On-a-Chip. The bus architecture is called the GGBA (General Global Bus Architecture.) The research findings presented in this report show that from two possible implementations for a system bus for this bus architecture, one of those would be the most advantageous based on factors such as bus latency, crosstalk, and bus area.