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dc.contributor.authorKrishnamurthy, Rajaram B.en_US
dc.contributor.authorYalamanchili, Sudhakar
dc.contributor.authorSchwan, Karsten
dc.contributor.authorWest, Richard
dc.date.accessioned2005-06-17T17:41:09Z
dc.date.available2005-06-17T17:41:09Z
dc.date.issued2002en_US
dc.identifier.urihttp://hdl.handle.net/1853/6546
dc.description.abstractWe present an architecture and hardware for scheduling gigabit packet streams in server clusters that combines a Network Processor datapath and an FPGA for use in server NICs and server cluster switches. Our architectural framework can provide EDF, static-priority, fair-share and DWCS native scheduling support for best-effort and real-time streams. This allows (i) interoperability of scheduling hardware supporting different scheduling disciplines and (ii) helps in providing customized scheduling solutions in server clusters based on traffic type, stream content, stream volume and cluster hardware using a hardware implementation of a scheduler running at wire-speeds. The architecture scales easily from 4 to 32 streams on a single Xilinx Virtex 1000 chip and can support 64-byte - 1500-byte Ethernet frames on a 1 Gbps link and 1500-byte Ethernet frames on a 10 Gbps link. A running hardware prototype of a stream scheduler in a Virtex 1000 PCI card can divide bandwidth based on user specifications and meet the temporal bounds and packet-time requirements of multi-gigabit links.en_US
dc.format.extent379728 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technologyen_US
dc.relation.ispartofseriesCC Technical Report; GIT-CC-02-39en_US
dc.subjectPacket scheduling algorithms
dc.subjectCluster servers
dc.subjectScalability
dc.subjectScheduling
dc.titleRASA (Reconfigurable Architectures for Scheduling Activities) Architecture and Hardware for Scheduling Gigabit Packet Streamsen_US
dc.typeTechnical Reporteng_US


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