Hardware/Software Deadlock Detection Algorithm and Implementation

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dc.contributor.author Shiu, Pun Hang en_US
dc.date.accessioned 2005-06-17T17:41:32Z
dc.date.available 2005-06-17T17:41:32Z
dc.date.issued 2002 en_US
dc.identifier.uri http://hdl.handle.net/1853/6550
dc.description.abstract This report introduces a new theorem and its proof about the problem of deadlock detection. First, we examine how to represent the problem of deadlock with a directed graph. Then, translation from a directed graph into a matrix is elaborated. The theorem and its proof are based on this matrix representation. By applying this theorem, we present a novel parallel deadlock detection algorithm, which we hypothesize has a run-time complexity of O[subscript hw](min(m,n)) in a parallel hardware implementation, where m, n are the number of processors and resources involved in deadlock detection respectively. en_US
dc.format.extent 725319 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.publisher Georgia Institute of Technology en_US
dc.relation.ispartofseries CC Technical Report; GIT-CC-02-46 en_US
dc.subject Deadlock detection
dc.subject Graphs
dc.subject Matrices
dc.subject Algorithms
dc.title Hardware/Software Deadlock Detection Algorithm and Implementation en_US
dc.type Technical Report eng_US


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