DESIGN, MODELING, OPTIMIZATION, AND BENCHMARKING OF INTERCONNECTS AND SCALING TECHNOLOGIES AND THEIR CIRCUIT AND SYSTEM LEVEL IMPACT
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This research focuses on the future of integrated circuit (IC) scaling technologies at the device and back end of line (BEOL) level. This work includes high level modeling of different technologies and quantifying potential performance gains on a circuit and system level. From the device side, this research looks at the scaling challenges and the future scaling drivers for conventional charge-based devices implemented at the 7nm technology node and beyond. It examines the system-level performance of stacking device logic in addition to tunneling field effect transistors (TFET) and their potential as beyond-CMOS devices. Finally, this research models and benchmarks BEOL scaling challenges and evaluates proposed technological advancements such as metal barrier scaling for copper interconnects and replacing local interconnects with ruthenium. Potential impact on performance, power, and area of these interconnect technologies is quantified for fully placed and routed circuits.