Bottom-up Process Development for High Throughput Electronic Device Fabrication

Abstract

Electronic device fabrication is inherently limited in throughput due to its 2-D nature. Despite this limitation, devices fabricated by the planar process are ubiquitous in every-day life. If the throughput of electronic devices could be pushed higher, the amount and types of material with computational capabilities will dramatically increase. To achieve such throughput, new processes for fabrication need to be developed. Specifically, shifting fabrication processes from 2-D to 3-D is the first step. To preserve high performance in devices, components need to maintain comparable quality to conventional electronic device fabrication processes. In this thesis, we develop a bottom-up process for masking nanoscale surfaces and structures for subsequent area selective deposition processes. We coin our process SCALES: Selective CoAxial Lithography via Etching of Surfaces, which is a combination of bottom-up polymerization followed by selective etching. We use vapor-liquid-solid (VLS) grown nanowires as a model system, where composition modulation is commonplace, and also done in a bottom-up fashion. VLS grown nanowires are single crystalline and do not compromise on electrical characteristics, thus being an ideal candidate for large scale electronic devices. The SCALES process is performed post nanowire growth via wet methods, where a polymer mask is created by selective etching, leveraging the composition modulation of the initial structure. We show that the SCALES process can successfully mask nanowires and act as a deposition mask for selective atomic layer deposition processes.