Modeling and simulation of FinFET SRAM reliability degraded by various wearout mechanisms
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The objective of this dissertation is to develop frameworks for performance-reliability degradation of FinFET SRAM due to wearout mechanisms including Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), Random Telegraph Noise (RTN), and Electromigration (EM). Since the first three mechanisms appear in front-end, while EM appears in back-end, the modeling and simulation methodologies designed for aging due to them are different. With respect to BTI, HCI, and RTN, a comprehensive framework for analysis on time-dependent performance-reliability degradation of an SRAM cache, considering cache configurations, process parameters and their variations, supply voltage, and aging, is developed. The framework consists of three parts: microprocessor emulation, activity extraction, and evaluation of performance-reliability metrics. Evaluation of performance-reliability metrics is implemented with a prediction engine involving regression models for the metrics, which evaluates degradation due to BTI, HCI, and RTN. The regression models not only enable more than 100× faster computation compared with SPICE simulations, but also protect intellectual property. This framework has been applied to study how SRAM I-Cache configurations, cell structure, inclusion of RTN and gate length variation, voltage scaling, and stress time affect the performance and reliability parameters, such as access time, leakage power, critical charge (Qcrit), and static noise margin (SNM). We have also studied the impact of configuration parameters on the soft error rate (SER) and the hit rate of the I-Cache, and the impact of single error correction and double error detection (SECDED) error correcting codes (ECC). On the other hand, a tool called CacheEM is designed for FinFET SRAM cache aging due to EM. CacheEM is based on a comprehensive framework including five parts: microprocessor emulation, memory cell array activity extraction, arrangement of current over long interconnects, evaluation on time-dependent hydrostatic stress and resistance shift of interconnects, and characterization on EM lifetime distribution of interconnects in cache memory. The first two steps are implemented with gem5 and cache simulation, respectively. It exports the number of read & write operations on each cell of a cache memory in microprocessor after running benchmarks. Then, based on the number of operations and the currents corresponding to each operation, CacheEM calculates the equivalent current distribution over each interconnect as the third step. The currents due to read & write operations are stored in models which have been pre-trained with regression algorithm. These models provide accurate predictions on corresponding currents under specific parameters such as temperature, supply voltage, and gate length et al. Afterwards, the samples of time-dependent hydrostatic stress and resistance shift over each interconnect are computed with incorporating the variations of effective activation energy and critical stress. The EM lifetime distribution of cache memory is extracted under pre-defined threshold values. In comparison of EM lifetime distributions, the impact of configuration parameters on EM reliability and performance of SRAM cache has been analyzed. The frameworks target at providing advice to SRAM cache designers. The decision on parameter selection for a cache depends on the designer’s requirements on various factors, such as acceptable performance, reliability, aging, area, complexity of hardware implementation, etc. Our frameworks can be utilized to provide cache designers with some potential advice on parameter selection with regard to reliability and performance.