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dc.contributor.authorAppelbe, William F.en_US
dc.contributor.authorDas, Raja
dc.contributor.authorHarmon, C. Reid, Jr.
dc.date.accessioned2005-06-17T17:52:33Z
dc.date.available2005-06-17T17:52:33Z
dc.date.issued1997en_US
dc.identifier.urihttp://hdl.handle.net/1853/6659
dc.description.abstractSpeculative execution of conditional branches has a high hardware cost, is limited by dynamic branch prediction accuracies, and does not scale well for increasingly superscalar architectures. Future branches are additional branch instructions that overcome the performance bottleneck of conventional branches. Future branch instructions includes a branch source address (the location of the impending conditional branch) as well as the branch target. The branch actually occurs when the program counter reaches the source address. If a future branch is executed before instruction fetching reaches the branch source, then there are no pipeline stalls or prediction necessary. Benchmark micro-architecture simulation studies show that at high superscalarities, losses to speculative execution consistently are higher than 10%, and these losses can be avoided by future branches. In addition, a hardware implementation of future branches for the PowerPC 604 has a very modest cost.en_US
dc.format.extent193184 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technologyen_US
dc.relation.ispartofseriesCC Technical Report; GIT-CC-97-33en_US
dc.subjectFuture branches
dc.subjectSpeculative execution paradigm
dc.titleFuture Branches -- Beyond Speculative Executionen_US
dc.typeTechnical Reporteng_US


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