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dc.contributor.authorHarmon, C. Reid, Jr.en_US
dc.contributor.authorAppelbe, William F.
dc.contributor.authorDas, Raja
dc.date.accessioned2005-06-17T17:52:44Z
dc.date.available2005-06-17T17:52:44Z
dc.date.issued1997en_US
dc.identifier.urihttp://hdl.handle.net/1853/6661
dc.description.abstractThis paper describes a new hardware approach to data and instruction prefetching for superscalar processors. The key innovation is instruction prefetching by predicting procedural control flow, and decoupling data and instruction prefetching. Simulation results show this method to recover 72% of unnecessarily lost cache cycles and to yield a great improvement (20-27%) over previous hardware prefetching techniques. The technique has a relatively small cost in hardware, and is intended to come between the processor and a level-1 cache.en_US
dc.format.extent317596 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technologyen_US
dc.relation.ispartofseriesCC Technical Report; GIT-CC-97-35en_US
dc.subjectPrefetching
dc.subjectSuper-scalar processors
dc.subjectControl-flow analysis
dc.titleIPU/LTB: A Method for Reducing Effective Memory Latencyen_US
dc.typeTechnical Reporteng_US


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