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dc.contributor.authorAltun, Oguzen_US
dc.date.accessioned2005-09-16T14:58:06Z
dc.date.available2005-09-16T14:58:06Z
dc.date.issued2005-04-18en_US
dc.identifier.urihttp://hdl.handle.net/1853/7104
dc.description.abstractA dual-mode second-order Multirate Multibit Sigma Delta (MM-SD) modulator is implemented in a 90nm digital CMOS process for application in the baseband path of RF receivers. Low power consumption is achieved through a new integrator structure and a dedicated timing scheme along with aggressive capacitor scaling in the second stage of the modulator loop. Fabricated prototype achieves 68.6dB peak Signal-to-Noise and Distortion ratio (SNDR) in the 200 kHz GSM band and requires 1.1mA of total current from a 1.5V supply. This dual-mode design also achieves 42.8dB SNDR in the 1.94 MHz WCDMA band with only 1.9mA of total current consumption.en_US
dc.format.extent1067977 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technologyen_US
dc.subjectLow-poweren_US
dc.subjectMixed-signal
dc.subjectLow voltage
dc.subjectSigma delta modulators
dc.titleA 1.5V Multirate Multibit Sigma Delta Modulator for GSM/WCDMA in a 90nm Digital CMOS Processen_US
dc.typeDissertationen_US
dc.description.degreePh.D.en_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.advisorCommittee Chair: Allen, Phillip E.; Committee Member: Ayazi, Farrokh; Committee Member: Laskar, Joy; Committee Member: Leach, Marshall W.; Committee Member: Morley, Tomen_US


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