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dc.contributor.authorSaint-Laurent, Martinen_US
dc.date.accessioned2005-09-16T15:34:08Z
dc.date.available2005-09-16T15:34:08Z
dc.date.issued2005-07-19en_US
dc.identifier.urihttp://hdl.handle.net/1853/7271
dc.description.abstractIntegrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems. The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.en_US
dc.format.extent3178694 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherGeorgia Institute of Technologyen_US
dc.subjectPhase-locked loopsen_US
dc.subjectInterlevel coupling noise
dc.subjectPower-performance tradeoff
dc.subjectSkew compensation
dc.subjectInterconnect
dc.subjectPower supply noise
dc.subjectSkew
dc.subjectClock distribution
dc.subjectLow-power design
dc.subjectJitter
dc.subjectMOSFET model
dc.subject.lcshTiming circuits Design and constructionen_US
dc.subject.lcshPhase-locked loopsen_US
dc.subject.lcshMetal oxide semiconductor field-effect transistorsen_US
dc.subject.lcshLow voltage integrated circuits Design and constructionen_US
dc.subject.lcshInterconnects (Integrated circuit technology)en_US
dc.titleModeling and Analysis of High-Frequency Microprocessor Clocking Networksen_US
dc.typeDissertationen_US
dc.description.degreePh.D.en_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.advisorCommittee Chair: Swaminathan, Madhavan; Committee Member: Davis, Jeffrey A.; Committee Member: Meindl, James D.en_US


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