Macromodeling of Nonlinear Driver and Receiver Circuits
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The signal integrity, power integrity, and timing analysis of todays high-speed digital systems are computationally exhaustive, both in terms of CPU memory required and simulation time consumed. One way to reduce this complexity is to use macromodels of the subcircuits comprising these high-speed digital systems. Since digital driver/receiver circuits have a major share in this computational load, modeling digital driver/receiver circuits accurately to capture their nonlinearity becomes a big challenge. The contribution of this thesis is to generate black-box macromodels of driver/receiver circuits that result in huge computational speed-up compared to actual transistor-level driver/receiver circuits and at the same time maintain high accuracy. It is always useful to have a black-box modeling approach as the modeling technique is independent of the knowledge of the internal logic of the circuit being modeled. This would make the modeling approach more robust and more applicable to a wide variety of circuits. Driver/receiver macromodels have been extended to multiple ports to take into account the effect of non-ideal power and ground nodes in this thesis.